verilator - Verilog HDL simulator

Property Value
Distribution NetBSD 7.0
Repository NetBSD i386
Package filename verilator-4.012.tgz
Package name verilator
Package version 4.012
Package release -
Package architecture i386
Package type tgz
Category cad
License gnu-lgpl-v3 OR artistic-2.0
Maintainer -
Download size 2.59 MB
Installed size 11.99 MB
Verilator is the fastest free Verilog HDL simulator, and outperforms
most commercial simulators. Verilator compiles synthesizable
SystemVerilog (generally not test-bench code), plus some SystemVerilog
and Synthesis assertions into single- or multithreaded C++ or
SystemC code. Verilator is designed for large projects where fast
simulation performance is of primary concern, and is especially
well suited to generate executable models of CPUs for embedded
software design teams.


Package Version Architecture Repository
verilator-4.012.tgz 4.012 amd64 NetBSD
verilator - - -


Type URL
Binary Package verilator-4.012.tgz
Source Package verilator

Install Howto

Install verilator tgz package:

# pkg_add verilator

See Also

Package Description
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