MyHDL-iverilog - Icarus Verilog cosimulation support for py-MyHDL

Property Value
Distribution NetBSD 7.1
Repository NetBSD amd64
Package filename MyHDL-iverilog-0.10.tgz
Package name MyHDL-iverilog
Package version 0.10
Package release -
Package architecture amd64
Package type tgz
Category cad python
License gnu-lgpl-v2.1
Maintainer -
Download size 6.30 KB
Installed size 15.05 KB
MyHDL is a Python package for using Python as a hardware
description language. Popular hardware description languages, like
Verilog and VHDL, are compiled languages. MyHDL with Python
can be viewed as a "scripting language" counterpart of such
languages. However, Python is more accurately described as a very
high level language (VHLL). MyHDL users have access to the
amazing power and elegance of Python for their modeling work.


Package Version Architecture Repository
MyHDL-iverilog-0.10.tgz 0.10 i386 NetBSD
MyHDL-iverilog - - -


Name Value
iverilog >= 10.1.1


Type URL
Binary Package MyHDL-iverilog-0.10.tgz
Source Package MyHDL-iverilog

Install Howto

Install MyHDL-iverilog tgz package:

# pkg_add MyHDL-iverilog

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